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Lattice Semiconductor
Convolutional Encoder User’s Guide
Functional Simulation with Modelsim
Both a sample script ?le (do_ce_fsim.do) and testbench template ?le (tb_ce_wrap_fsim.v) are provided with the
Convolutional Encoder core release. For additional details refer to the readme.html ?le in the Convolutional
Encoder core release directory.
Place and Route
Place and route engines are included in the ispLEVER software. The place and route options are available inside
the Constraint Editor. If an OEM synthesis tool is used for design synthesis, the same project can be used to com-
plete the design place and route. If a non-OEM synthesis tool is used for design synthesis, a project must be cre-
ated using the ispLEVER Project Navigator.
ispLEVER Software Flow for ORCA Devices
1. Create a project directory.
2. Copy the synthesized design EDIF ?le and the Convolutional Encoder core netlist to the project directory.
3. Launch the ispLEVER software. Figure 16 shows the ispLEVER Project Navigator Window .
Figure 16. ispLEVER Project Navigator Window
4. Select File > New Project and to create a new project or browse the project directory. All the design ?les will
be generated in this directory. Type project name and select EDIF as a project type.
5. Double click the device name in the Process Window of the Project Navigator and select the device.
6. Select Source > Import . The Import File Dialog Box is shown in Figure 17. Enter the EDIF ?le name and
click Open . The Import EDIF Dialog Box is shown in Figure 18. Select the EDIF vendor type and click OK .
The EDIF ?le will be added to the project.
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